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NEC PD17062 User Manual

Page 103

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103

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PD17062

10.5.7 PLL Data Register

Fig. 10-10 shows how the PLL data register functions.

The PLL data register sets the frequency division ratio of the PLL frequency synthesizer. For the pulse

swallow method, all 16 bits are valid, the 12 high-order bits are set in the program counter, and the remaining

four low-order bits are set in the swallow counter.

Fig. 10-10 PLL Data Register

DBF3

0CH

DBF2

0DH

DBF1

0EH

DBF0

0FH

b

15

b

14

b

13

b

12

b

11

b

10

b

9

b

8

b

7

b

6

b

5

b

4

b

3

b

2

b

1

b

0

b

7

b

6

b

5

b

4

b

3

b

2

b

1

b

0

PLLR

41H

PLL frequency synthesizer frequency division ratio

16

b

15

b

14

b

13

b

12

b

11

b

10

b

9

b

8

256 (0100H)

x

0 (0000H)

2

16

- 1 (0FFFFH)

Not to be set.

Frequency division ratio N:N = x

PLL frequency

synthesizer

Symbol

Peripheral

address

Peripheral hardware

Name

Data buffer

Symbol

Address

Bit

Data

Transfer data

GET

PUT

Name

PLLR data

register

Peripheral register

Valid data