9 pll reference mode selection register (13h) – NEC PD17062 User Manual
Page 79
79
µ
PD17062
9.9 PLL REFERENCE MODE SELECTION REGISTER (13H)
9.10 SETTING OF INT
NC
PIN ACCEPTANCE PULSE WIDTH (15H)
b
3
b
2
b
1
b
0
PLLRFCK3
PLLRFCK2
PLLRFCK0
13H
PLLRFCK1
0
0
1
0
0
0
1
1
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
0
6.25 kHz
12.5 kHz
25 kHz
PLL disabled
Not to be set
Reference frequency f
r
setting
Fixed at 1
b
3
b
2
b
1
b
0
INTNCMD3
INTNCMD2
INTNCMD0
15H
INTNCMD1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Edge (no noise canceler)
200
s
2 ms
Setting of INT
NC
pin acceptance pulse width
Fixed at 0
4 ms
400 s
µ
µ