NEC PD17062 - Manual (Page 181)

181
µ
PD17062
Fig. 14-6 Relationship Between Power-on Reset and CE Reset
(a) When V
DD
and CE pin raised simultaneously
(b) When CE pin raised in halt state
(c) When CE pin raised after power-on reset
5 V
0 V
Opera-
tion
stopped
V DD
CE
Power-on reset
Program start
Power-on clear voltage 3.5 V
Halt state
50ms Normal operation
Timer carry FF
set pulse
5 V
0 V
V
DD
CE
Power-on reset
Program start
Power-on clear voltage 3.5 V
Halt state
50 ms Normal operation
Timer carry FF
set pulse
Opera-
tion
stopped
0 V
V DD
CE
Timer carry FF
set pulse
Power-on reset
Program start
Power-on clear voltage
3.5 V
Halt state
50 ms Normal operation
CE reset
Program start
Opera-
tion
stopped
5 V