NEC PD17062 - Manual (Page 179)

179
µ
PD17062
Fig. 14-5 Power-on Reset and V DD
(a) During normal operation (including halt state)
(b) At clock-stop
(c) When V DD rises from 0 V
5 V
0 V
“H”
Normal operation
Device operation
stopped
X OUT
V
DD
CE
Power-on
clear signal
Power-on clear release
Oscillation start Power-on reset
Program starts from address 0
Halt state
50 ms
Power-on clear voltage 3.5 V
5 V
Clock-stop
Device operation
stopped
X OUT
V DD
CE
Power-on
clear signal
Power-on clear release
Oscillation start Power-on reset
Program starts from address 0
Halt state
50 ms
2.2 V
Power-on clear voltage
3.5 V
STOP 0000B
Normal operation
“L”
5 V
0 V
Device operation stopped
X OUT
V
DD
CE
Power-on
clear signal
Power-on clear release
Oscillation start Power-on reset
Program starts from address 0
Halt state
50 ms
3.5 V Power-on clear voltage
“L”