NEC PD17062 User Manual
Page 178
178
µ
PD17062
14.4.1 Power-on Reset at Normal Operation
Fig. 14-5 (a) shows power-on reset at normal operation.
As shown in Fig. 14-5 (a), when the V
DD
drops below 3.5 V, the power-on clear signal is output and operation
of the device stops regardless of the input level of the CE pin.
When V
DD
then rises to 3.5 V or greater, after a 50 ms halt, the program starts from address 0000H.
Normal operation refers to the state in which the clock-stop instruction is not used. This also includes the
halt state set by the halt instruction.
14.4.2 Power-on Reset in Clock-Stop State
Fig. 14-5 (b) shows power-on reset in the clock-stop state.
As shown in Fig. 14-5 (b), when V
DD
drops below 2.2 V, the power-on clear signal is output and device
operation stops.
However, since the device is in the clock-stop state, its operation apparently does not change.
When V
DD
rises to 3.5 V or greater, after a 50 ms halt, the program starts from address 0000H.
14.4.3 Power-on Reset When V
DD
Rises From 0 V
Fig. 14-5 (c) shows power-on reset when V
DD
rises from 0 V.
As shown in Fig. 14-5 (c), the power-on clear signal is being output while V
DD
is rising from 0 to 3.5 V.
When V
DD
rises above the power-on clear voltage, the crystal oscillation circuit starts and after a 50 ms halt,
the program starts from address 0000H.