Avago Technologies LSI53C1020 - Manual (Page 99)

PCI Configuration Space Register Descriptions 4-21
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Register: 0xXX
Power Management Control/Status
Read/Write
PME_Status 15
The PCI function clears this bit because the LSI53C1020
does not support PME signal generation from D3
cold
.
Data_Scale [14:13]
The PCI function clears these bits because the
LSI53C1020 does not support the Power Management
Data register.
Data_Select [12:9]
The PCI function clears these bits because the
LSI53C1020 does not support the Power Management
Data register.
PME_Enable 8
The PCI function clears this bit because the LSI53C1020
does not provide a PME signal and disables PME asser-
tion.
Reserved [7:2]
This field is reserved.
Power State [1:0]
These bits determine the current power state of the
LSI53C1020. Power states are as follows:
15 14 13 12 9 8 7 2 1 0
Power Management Control/Status
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0b00 D0
0b01 D1
0b10 D2
0b11 D3
hot