Avago Technologies LSI53C1020 - Manual (Page 111)

I/O Space and Memory Space Register Descriptions 4-33
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Table 4.4 defines the PCI Memory Space [0] address map.
Table 4.5 defines the PCI Memory Space [1] address map.
A bit level description of the PCI Memory and PCI I/O Spaces follows.
Table 4.4 PCI Memory [0] Address Map
31 0 Offset Page
System Doorbell 0x0000 4-34
Write Sequence 0x0004 4-35
Host Diagnostic 0x0008 4-36
Test Base Address 0x000C 4-37
Reserved 0x0010–0x002F –
Host Interrupt Status 0x0030 4-40
Host Interrupt Mask 0x0034 4-41
Reserved 0x0038–0x003F –
Request Queue 0x0040 4-42
Reply Queue 0x0044 4-42
Reserved 0x0048–0x007F –
Shared Memory
0x0080 –
0x(Sizeof(Mem0)-1)
–
Table 4.5 PCI Memory [1] Address Map
31 0
Diagnostic Memory
0x0000 –
0x(Sizeof(Mem1)
−
1)