Avago Technologies LSI53C1020 - Manual (Page 79)

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual 4-1
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Chapter 4
PCI Host Register
Description
This chapter describes the PCI host register space. This chapter
contains the following sections:
•
Section 4.1, “PCI Configuration Space Register Descriptions”
•
Section 4.2, “I/O Space and Memory Space Register Descriptions”
The register map at the beginning of each register description provides
the default bit settings for the register. Shading indicates a reserved bit
or register. Do not access reserved address areas.
The PCI System Address space consists of three regions: Configuration
Space, Memory Space, and I/O Space. PCI Configuration Space
supports the identification, configuration, initialization, and error
management functions for the LSI53C1020 PCI device.
PCI Memory Space [0] and Memory Space [1] form the PCI Memory
Space. PCI Memory Space [0] provides normal system accesses to
memory, and PCI Memory Space [1] provides diagnostic memory
accesses. PCI I/O Space provides normal system access to memory.
Note: In this chapter, LSI53C1020 refers to both the LSI53C1020
SCSI controller and the LSI53C1020A SCSI controller,
unless specifically noted.
4.1 PCI Configuration Space Register Descriptions
This section provides bit level descriptions of the Fusion-MPT PCI
Configuration Space registers.
Table 4.1 defines the PCI Configuration
Space registers. The LSI53C1020 enables, orders, and locates the PCI
extended capability register structures (Power Management, Messaged
Signaled Interrupts, and PCI-X) to optimize device performance. The
LSI53C1020 does not hard code the location and order of the PCI