Avago Technologies LSI53C1020 - Manual (Page 83)

PCI Configuration Space Register Descriptions 4-5
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Enable Memory Space 1
This bit controls the ability of the PCI function to respond
to Memory Space accesses. Setting this bit allows the
LSI53C1020 to respond to Memory Space accesses at
the address range specified by the
Memory [0] Low ,
Memory [0] High , Memory [1] Low , Memory [1] High , and
Expansion ROM Base Address registers. Clearing this bit
disables the PCI function’s response to Memory Space
accesses.
Enable I/O Space 0
This bit controls the PCI function’s response to I/O Space
accesses. Setting this bit enables the PCI function to
respond to I/O Space accesses at the address range the
PCI Configuration Space
I/O Base Address register spec-
ifies. Clearing this bit disables the PCI function’s
response to I/O Space accesses.
Register: 0x06–0x07
Status
Read/Write
Reads to this 16-bit register behave normally. To clear a bit location that
is currently set, write the bit to one (1). For example, to clear bit 15 when
it is set, without affecting any other bits, write 0x8000 to the register.
Detected Parity Error (from Slave) 15
This bit is set according to the PCI Local Bus Specifica-
tion, Revision 2.2, and PCI-X Addendum to the PCI Local
Bus Specification, Revision 1.0a.
Signaled System Error 14
The LSI53C1020 PCI function sets this bit when assert-
ing the SERR/ signal.
Received Master Abort (from Master) 13
A master device sets this bit when a Master Abort com-
mand terminates its transaction (except for Special
Cycle).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
Status
0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0