Avago Technologies LSI53C1020 User Manual

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2-14

Functional Description

Version 2.4

line. The LSI53C1020 supports this command when operating in the PCI
mode.

2.3.2.16

Memory Read Block Command

The LSI53C1020 uses this command to read from memory. The
LSI53C1020 supports this command when operating in the PCI-X mode.

2.3.2.17

Memory Write and Invalidate Command

This command is identical to the Memory Write command, except it
additionally guarantees a minimum transfer of one complete cache line.
The master uses this command when it intends to write all bytes within
the addressed cache line in a single PCI transaction unless interrupted
by the target. This command requires implementation of the PCI

Cache

Line Size

and Invalidate command instead of a Memory Write command and
supports this command when operating in the PCI bus mode.

Alignment – The LSI53C1020 uses the calculated line size value to
determine if the current address aligns to the cache line size. If the
address does not align, the LSI53C1020 bursts data using a noncache
command. If the starting address aligns, the LSI53C1020 issues a
Memory Write and Invalidate command using the cache line size as the
burst size.

Multiple Cache Line Transfers – The Memory Write and Invalidate
command can write multiple cache lines of data in a single bus
ownership. The LSI53C1020 issues a burst transfer as soon as it
reaches a cache line boundary. The PCI Local Bus specification states
that the transfer size must be a multiple of the cache line size. The
LSI53C1020 selects the largest multiple of the cache line size based on
the transfer size. When the DMA buffer contains less data than the value

Cache Line Size

Write command on the next cache boundary to complete the data
transfer.

2.3.2.18

Memory Write Block Command

The LSI53C1020 uses this command to burst data to memory. The
LSI53C1020 supports this command when operating in the PCI-X bus
mode.

This manual is related to the following products:

LSI53C1020A