Avago Technologies LSI53C1020 - Manual (Page 166)

IX-6 Index
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
memory space
description 4-32
message address register 4-25
message control register 4-23
message data register 4-26
message passing technology 1-9 , 2-1
message queues 2-7
message signalled interrupts 2-15
message upper address register 4-25
MFA
reply 4-42
rerequest 4-42
minimum grant register 4-18
MSI 1-10 , 1-11 , 2-15
capability ID register 4-22
enable bit 4-24
message address 4-25
message data 4-26
message upper address register 4-25
multiple message 4-24
multiple message capable 4-24
next pointer register 4-23
multi-ICE 2-29
multiple cache line transfers 2-14
multiple message capable 4-24
multiple message enable 4-23
N
NC 3-1 , 3-18
new capabilities bit 4-6
no connect 3-1
normal/fast memory (128 Kbytes)
single byte access read cycle 5-12 , 5-16
single byte access write cycle 5-14 , 5-18
NVSRAM 1-3 , 2-2 , 2-5 , 2-23 , 3-12 , 3-13
block diagram 2-26
integrated mirroring 2-26
interface 3-12
select 3-20
sense 3-19
write journaling 2-26
O
operating conditions 5-2
operating free air temperature 5-2
output signals 5-6
P
P1 line 2-19
paced transfers 1-2 , 2-18
package drawing 5-20 , 5-21
packetized protocol 1-2 , 1-9 , 2-20
PAR 3-5 , 5-5
PAR64 3-5 , 5-5
parallel protocol request 2-18 , 2-21
parity error 4-6
passive termination 2-23
PC2001 system design guide 1-10 , 2-16
PCI 1-11 , 2-7
33 MHz 5-9
64-bit 3-19 , 3-20
66 MHz 3-19 , 3-20 , 5-9
66 MHz capable bit 4-6
address and data signals 3-5
address/data bus 3-18 , 4-30
addressing 2-8
alias to memory read block command 2-12 ,
2-13
alias to memory write block command 2-12
arbitration 2-15
arbitration signals 3-6
benefits 1-6
bidirectional signals 5-5
bus commands 2-9
bus interface 3-4
cache line size register 2-14
cache mode 2-15
CLK 5-9
command
configuration read 2-8 , 2-10 , 2-12
configuration write 2-8 , 2-10 , 2-12
dual address cycle 2-10 , 2-13
dual address cycles 1-10 , 2-8
I/O read 2-10 , 2-11
I/O write 2-10 , 2-11
interrupt acknowledge 2-10
memory read 2-11
memory read block 1-10 , 2-10 , 2-12 , 2-14
memory read dword 1-10 , 2-10 , 2-11
memory read line 1-10 , 2-10 , 2-13
memory read multiple 1-10 , 2-10 , 2-13
memory write 2-10 , 2-11
memory write and invalidate 1-10 , 2-10 ,
2-14