Avago Technologies LSI53C1020 - Manual (Page 161)

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual IX-1
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Index
Numerics
12 mA output signals 5-6
133 MHz 1-10
133 MHz capable bit 4-30
133 MHz PCI-X 1-3 , 3-19 , 3-20 , 5-9
133 MHz PCI-X bit 4-30
33 MHz PCI 5-9
64-bit address capable bit 4-23
64-bit device bit 4-30
64-bit enable bit 3-20
64-bit PCI 1-3 , 1-10 , 3-19 , 3-20
66 MHz capable bit 3-20 , 4-6
66 MHz PCI 3-19 , 3-20 , 5-9
66 MHz PCI-X 5-9
8 mA output signals 5-6
A
A_LED/ 2-5 , 3-16
absolute maximum stress ratings 5-2
AC characteristics 5-9
ACK64/ 3-6 , 5-5
active low 3-1
active termination 2-23
AD[31:0] 5-5
AD[63:0] 3-5 , 5-5
address
diagnostic read/write 4-39
latches 3-13
address reply 2-7
address/data bus 3-18 , 4-30
air temperature 5-2
alias to memory read block 2-10 , 2-12 , 2-13
alias to memory write block 2-10 , 2-12
alignment 2-14
ALT_INTA/ 2-15 , 3-8 , 4-24 , 4-41 , 5-6
analog voltage 5-2
arbitration 2-15
ARM Multi-ICE 1-12
ARM966E-S 1-3 , 1-9 , 2-4 , 2-6 , 3-9 , 4-36
aux_current bit 4-20
B
ball grid array 5-20 , 5-21
base address register
I/O 2-4 , 4-9
memory [0] 4-10
memory [1] 4-11
bidirectional signals 5-5
BIOS 2-8 , 2-27
bit
133 MHz capable 4-30
64-bit address capable 4-23
64-bit device 4-30
66 MHz capable 4-6
aux current 4-20
bus number 4-30
D1 support 4-20
D2 support 4-20
data parity error recovery enable 4-28
data parity error reported 4-6
data scale 4-21
data select 4-21
designed maximum cumulative read size 4-29
designed maximum memory read byte count
4-29
designed maximum outstanding split transac-
tions 4-29
detected parity error (from slave) 4-5
device complexity 4-30
device number 4-31
device specific initialization 4-20
DEVSEL/ timing 4-6
diagnostic memory enable 4-37
diagnostic read/write enable 4-36