Avago Technologies LSI53C1020 - Manual (Page 13)

Contents xiii
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Tables
2.1 PCI/PCI-X Bus Commands and Encodings 2-10
2.2 Power States 2-16
2.3 Flash ROM Size Programming 2-24
2.4 Flash Signature Value 2-26
2.5 PCI Configuration Record in Serial EEPROM 2-27
2.6 20-Pin Multi-ICE Header Pinout 2-30
3.1 PCI System Signals 3-4
3.2 PCI Address and Data Signals 3-5
3.3 PCI Interface Control Signals 3-6
3.4 PCI Arbitration Signals 3-6
3.5 PCI Error Reporting Signals 3-7
3.6 PCI Interrupt Signal 3-7
3.7 PCI-Related Signals 3-8
3.8 SCSI Bus Clock Signal 3-9
3.9 SCSI Channel Interface Signals 3-9
3.10 SCSI Channel Control Signals 3-11
3.11 Flash ROM/NVSRAM Interface Signals 3-12
3.12 Serial EEPROM Interface Signals 3-13
3.13 ZCR Configuration Signals 3-13
3.14 JTAG, ICE, and Debug Signals 3-14
3.15 LSI Logic Test Signals 3-15
3.16 GPIO and LED Signals 3-16
3.17 Power and Ground Pins 3-16
3.18 No Connect Pins 3-18
3.19 MAD Power-On Sense Pin Options 3-19
3.20 Flash ROM Size Programming 3-21
3.21 Pull-Up and Pull-Down Signal Conditions 3-22
4.1 LSI53C1020 PCI Configuration Space Address Map 4-2
4.2 Subsystem ID Register Download Conditions and Values 4-15
4.3 PCI I/O Space Address Map 4-32
4.4 PCI Memory [0] Address Map 4-33
4.5 PCI Memory [1] Address Map 4-33
5.1 Absolute Maximum Stress Ratings 5-2
5.2 Operating Conditions 5-2