Avago Technologies LSI53C1020 - Manual (Page 163)

Index IX-3
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
D1 2-16 , 4-21
D1 support bit 4-20
D2 2-16 , 2-17 , 4-21
D2 support bit 4-20
D3 2-16 , 2-17 , 4-21
DAC 1-10 , 2-8 , 2-10 , 2-13
data
diagnostic read/write register 4-38
EEPROM 3-13
parity error recovery enable bit 4-28
parity error reported bit 4-6
scale bit 4-21
select bit 4-21
datapath engine 2-6
DC characteristics 5-1
debug signals 3-14
debugging 1-12
delay filter 5-8
designed maximum cumulative read size bit 4-29
designed maximum memory read byte count bit
4-29
designed maximum outstanding split transactions
bit 4-29
detected parity error (from slave) bit 4-5
device complexity bit 4-30
device driver stability 1-6
device ID register 4-3
device number bit 4-31
device specific initialization bit 4-20
DEVSEL/ 3-6 , 5-5
DEVSEL/ timing bit 4-6
diagnostic memory 4-32
diagnostic memory enable bit 4-37
diagnostic read/write address register 4-35 , 4-36 ,
4-39
diagnostic read/write data register 4-35 , 4-36 ,
4-38 , 4-39
diagnostic read/write enable bit 4-36
diagnostic write enable bit 4-35 , 4-36 , 4-39
DIFFSENS 2-22 , 3-10 , 5-4
DIS_PCI_FSN/ 3-15 , 3-22 , 5-6
DIS_SCSI_FSN/ 3-15 , 3-22 , 5-6
DisARM bit 4-36 , 4-37
DMA 1-11 , 2-4 , 2-6 , 2-15
arbiter and router 2-4
domain validation 1-2 , 1-7 , 1-12 , 2-22
doorbell 2-7 , 2-8
host 4-34
interrupt mask bit 4-41
status bit 4-40
system 4-34 , 4-40
system interface 2-7
system interrupt bit 4-40
double transition clocking 1-2 , 2-18
drawing
mechanical 5-31
package 5-20 , 5-21
drive strength 1-8 , 2-20 , 2-22
driver
LVD 5-3
DT clocking 1-2 , 2-18
DT data phase 2-18
dual address cycles command 1-10 , 2-8 , 2-10 ,
2-13
E
EEPROM 2-5 , 2-6 , 2-27 , 3-13 , 3-20 , 3-22
configuration record 2-27
download enable 3-19
interface 2-27 , 3-13
electrostatic discharge 5-2
enable
bus mastering bit 4-4
diagnostic memory bit 4-37
diagnostic write bit 4-36
I/O space bit 4-5
memory space bit 4-5
MSI bit 4-24
parity error response bit 4-4
write and invalidate bit 4-4
ESD 1-12 , 5-2 , 5-8
expansion ROM base address 4-5
expansion ROM base address register 4-15
expansion ROM enable bit 4-15
external
clock 5-9
memory controller 2-5
memory interface 2-23
memory interface timing diagrams 5-11
F
ferrite bead 3-17
fibre channel 1-5 , 1-11
FIFO
DMA 2-4