Avago Technologies LSI53C1020 - Manual (Page 115)

I/O Space and Memory Space Register Descriptions 4-37
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
TTL Interrupt 3
Setting this bit configures PCI INTA/ as a TTL output.
Clearing this bit configures PCI INTA/ as an open-drain
output. Use this bit for test purposes only.
Reset Adapter 2
Setting this write-only bit causes a hard reset within the
LSI53C1020. The bit self-clears after eight PCI clock
periods. After deasserting this bit, the IOP ARM proces-
sor executes from its default reset vector.
DisARM 1
Setting this bit disables the ARM processor.
Diagnostic Memory Enable 0
Setting this bit enables diagnostic memory accesses
through PCI Memory Space [1]. Clearing this bit disables
diagnostic memory accesses to PCI Memory Space [1]
and returns 0xFFFF on reads.
Register: 0x0C
Test Base Address
Read/Write
The Test Base Address register specifies the base address for Memory
Space [1] accesses.
Test Base Address [31:16]
The number of significant bits is determined by the size
of the PCI Memory Space [1] in the serial EEPROM.
Reserved [15:0]
This field is reserved.
31 16 15 0
Test Base Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0