Avago Technologies LSI53C1020 User Manual
Page 145
Pinout Information and Mechanical Drawings
5-25
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Table 5.21
LSI53C1020 456-Pin Pinout by BGA Position (Cont.)
AE11
AD26
AE12
AD25
AE13
AD21
AE14
AD18
AE15
IRDY/
AE16
TRDY/
AE17
PERR/
AE18
C_BE1/
AE19
AD14
AE20
AD9
AE21
C_BE0/
AE22
AD6
AE23
AD1
AE24
VDDC
AE25
GPIO1
AE26
VDD_IO
AF1
VDD_IO
AF2
VSS_IO
AF3
TDI_CHIP
AF4
BZVDD
AF5
VDD_IO
AF6
VSS_IO
AF7
ALT_INTA/
AF8
AD30
AF9
VDD_IO
AF10
VSS_IO
AF11
AD20
AF12 PCI5VBIAS
AF13
VDD_IO
AF14
VSS_IO
AF15
VDDC
AF16
AD19
AF17
VDD_IO
AF18
VSS_IO
AF19
PAR
AF20
AD10
AF21
VDD_IO
AF22
VSS_IO
AF23
AD7
AF24
AD3
AF25
VDD_IO
AF26
VSS_IO
Ball
Signal
Ball
Signal
P3
SD7+
P4
SDP0-
P5
SDP0+
P11
VSS_IO
P12
VSS_IO
P13
VSS_IO
P14
VSS_IO
P15
VSS_IO
P16
VSS_IO
P22
AD42
P23
AD41
P24
AD39
P25
AD38
P26
VSS_IO
R1
RBIAS
R2
SD5+
R3
VSS_IO
R4
SD7-
R5
SD6+
R11
VSS_IO
R12
VSS_IO
R13
VSS_IO
R14
VSS_IO
R15
VSS_IO
R16
VSS_IO
R22
AD43
R23
AD40
R24
VDD_IO
R25
AD44
R26
AD36
T1
VDDBIAS
T2
SD5-
T3
NC
T4
SD4+
T5
SD6-
T11
VSS_IO
T12
VSS_IO
T13
VSS_IO
T14
VSS_IO
T15
VSS_IO
T16
VSS_IO
T22
AD47
T23
AD46
T24
VSS_IO
T25
AD45
T26
AD37
U1
VSS_IO
U2
SD4-
U3
SD2+
U4
SD3+
U5
SD3-
U22
AD55
U23
AD49
U24
AD52
U25
AD48
U26
VDD_IO
V1
VDD_IO
V2
SD2-
V3
SD0+
V4
SD1-
V5
SD1+
V22
AD56
V23
AD53
V24
AD54
V25
AD51
V26
VSS_IO
W1
SDP1+
W2
SDP1-
W3
VSS_IO
W4
SD0-
W5
SD15+
W22
AD63
W23
AD59
W24
NC
W25 PCI5VBIAS
W26
AD50
Y1
SD15-
Y2
SD14+
Y3
VDD_IO
Y4
IDDTN
Y5
TMS_ICE
Y22
PCI5VBIAS
Y23
C_BE5/
Y24
VSS_IO
Y25
AD58
Y26
AD57
AA1
VSS_IO
AA2
SD14-
AA3
SD13+
AA4
TCK_ICE
AA5
RTCK_ICE
AA22
JtagMode
AA23
C_BE7/
AA24
PAR64
AA25
AD60
AA26
VDD_IO
AB1
VDD_IO
AB2
SD13-
AB3
TDI_ICE
AB4
TRST_ICE/
AB5
VSSC
AB6
TESTACLK
AB7
VSSC
AB8
VSSC
AB9
NC
AB10
RST/
AB11
AD28
AB12
AD24
AB13
C_BE3/
AB14
C_BE2/
AB15
FRAME/
AB16
STOP/
AB17
AD12
AB18
AD11
AB19
AD5
AB20
ACK64/
AB21
VDDA
AB22
PCI5VBIAS
AB23
VSSC
AB24
VSSC
AB25
AD62
AB26
VSS_IO
AC1
SD12+
AC2
NC
AC3
VSS_IO
AC4
DIS_SCSI_FSN/
AC5
IOPD_GNT
AC6
TCK_CHIP
AC7
VDDC
AC8
INTA/
AC9
ScanRstDis
AC10
PCI5VBIAS
AC11
AD27
AC12
AD23
AC13
IDSEL
AC14
AD16
AC15
AD17
AC16
DEVSEL/
AC17
SERR/
AC18
AD13
AC19
AD8
AC20
AD2
AC21
AD0
AC22
CLK
AC23
GPIO0
AC24
VDD_IO
AC25
C_BE6/
AC26
AD61
AD1
SD12-
AD2
TDO_ICE
AD3
VDDC
AD4
VDD_IO
AD5
TST_RST/
AD6
TDO_CHIP
AD7
VSS_IO
AD8
VDD_IO
AD9
PCI5VBIAS
AD10
REQ/
AD11
VSS_IO
AD12
VDD_IO
AD13
AD22
AD14
VSSC
AD15
VSS_IO
AD16
VDD_IO
AD17
AD15
AD18 PCI5VBIAS
AD19
VSS_IO
AD20
VDD_IO
AD21
AD4
AD22
REQ64/
AD23
VSS_IO
AD24
VSSA
AD25
VDDC
AD26
C_BE4/
AE1
VSS_IO
AE2
TESTHCLK
AE3
VDDC
AE4
TMS_CHIP
AE5
BZRESET
AE6
PCI5VBIAS
AE7
NC
AE8
GNT/
AE9
AD31
AE10
AD29
Ball
Signal
Ball
Signal
Ball
Signal