Avago Technologies LSI53C1020 - Manual (Page 171)

Index IX-11
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
TMS_ICE 3-14
TN 3-15
TRDY/ 3-6
TRST_ICE/ 3-14
TST_RST/ 3-14
VDD_IO 3-16
VDDA 3-17
VDDBIAS 3-9
VDDC 3-17
VSS_IO 3-17
VSSA 3-17
VSSC 3-17
ZCR_EN/ 3-13
signal drive strength 2-20 , 2-22
signal list 5-22 , 5-24 , 5-27 , 5-29
signalled system error bit 4-5
signals
bidirectional 5-5
flash ROM/NVSRAM interface 3-12
GPIO 3-16
ground 3-16
input 5-6
LED 3-16
PCI address and data 3-5
PCI arbitration 3-6
PCI error reporting 3-7
PCI interface control 3-6
PCI interrupt 3-7
PCI system 3-4
PCI-related 3-8
power 3-16
power-on sense 3-18
pull-ups and pull-downs 3-22
SCSI channel control 3-11
serial EEPROM interface 3-13
test interface 3-14
zero channel RAID interface 3-13
signature recognition 2-25
single ended SCSI 2-22 , 5-7
SIO+- 3-11 , 5-3 , 5-4
SISL 1-10
skew compensation 1-2 , 1-7 , 1-9 , 2-21
slew rate 1-8 , 1-9 , 2-22 , 5-8 , 5-9
SMSG+- 3-11 , 5-3 , 5-4
SPARE[13:12] 3-15
special cycle command 2-10 , 2-11 , 4-5
split completion command 1-10 , 2-10 , 2-13
split completion discarded bit 4-30
split completion error 4-29
split completion received error message 4-29
split completion unexpected 4-30
split transaction 1-10 , 4-29
SREQ+- 3-11 , 5-3 , 5-4
SRST+- 3-11 , 5-3 , 5-4
SSEL+- 3-11 , 5-3 , 5-4
status
IOP doorbell bit 4-40
register 4-4 , 4-5 , 4-28
STOP/ 3-6 , 5-5
stress ratings 5-2
subsystem ID 2-27 , 3-20 , 4-15
subsystem ID register 4-14
subsystem vendor ID 2-27 , 3-20
subsystem vendor ID register 4-13
supply current 5-2
supply voltage 5-2
SureLINK 1-2 , 1-7 , 1-12 , 2-22
system address space 4-1
system application 1-4
system BIOS 2-8 , 2-27
system doorbell 2-15 , 4-34 , 4-40
system doorbell interrupt bit 4-40
system doorbell register 4-34
system interface 2-4 , 2-15
bus mastering function 2-15
doorbell 2-7
T
Ta 5-2
target abort 4-6
TCK_CHIP 3-14 , 3-22 , 5-6
TCK_ICE 2-30 , 3-14 , 3-22 , 5-6
TDI_CHIP 3-14 , 3-22 , 5-6
TDI_ICE 2-30 , 3-14 , 3-22 , 5-6
TDO_CHIP 3-14 , 5-6
TDO_ICE 2-30 , 3-14 , 5-6
temperature
junction 5-2
lead 5-2
operating free air 5-2
storage 5-2
termination 2-23
test base address register 4-37
test condition 5-8
test interface 2-29 , 3-14
testability 1-12