Avago Technologies LSI53C1020 - Manual (Page 76)

3-20 Signal Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
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MAD[15], 133 MHz PCI-X – By default, internal logic pulls this pin
LOW to enable 133 MHz PCI-X operation and to set the
133 MHz Capable bit in the
PCI-X Status register. Pulling this pin
HIGH disables 133 MHz PCI-X operation and clears the
133 MHz Capable bit in the
PCI-X Status register.
•
MAD[14], 64-bit PCI – By default, internal logic pulls this pin LOW
to enable 64-bit PCI operation and to set the 64-bit Enable bit in the
PCI-X Status register. Pulling this pin HIGH configures the PCI
connection as a 32-bit connection and clears the 64-bit Enable bit in
the
PCI-X Status register.
•
MAD[13], 66 MHz PCI – By default, internal logic pulls this pin LOW
to enable 66 MHz PCI operation on the LSI53C1020 and to set the
66 MHz Capable bit in the PCI
Status register. Pulling this pin HIGH
disables 66 MHz PCI operation and clears the 66 MHz Capable bit
in the PCI
Status register.
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MAD[12:11], Reserved.
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MAD[10], ID Control – By default, internal logic pulls this pin LOW.
Pulling this signal LOW either allows the serial EEPROM to program
bit 15 of the
Subsystem ID register or allows this bit to default to 0b0.
Pulling this pin HIGH sets this bit to 0b1.
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MAD[9:8], Reserved.
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MAD[7], Serial EEPROM Download Enable – By default, internal
logic pulls this pin LOW to enable the download of PCI configuration
information from the serial EEPROM. Pulling this pin HIGH disables
the download of the PCI configuration information from the serial
EEPROM. Disabling the download of PCI configuration information
defaults the
Subsystem Vendor ID register to 0x1000 and defaults
the Subsystem ID register to either 0x1000 if MAD[10] is pulled LOW
or to 0x8000 if MAD[10] is pulled HIGH.
•
MAD[6], IOP Boot Enable – By default, internal logic pulls this pin
LOW. In the default mode, the IOP starts the boot process and
downloads firmware from the Flash ROM. Pulling this pin HIGH
causes the IOP to await a firmware download from the host system.
•
MAD[5:4], Reserved.
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MAD[3], NVSRAM Select – By default, internal logic pulls this pin
LOW, which has no effect on the LSI53C1020. Pulling this pin HIGH
configures the external memory interface as an NVSRAM interface.