Avago Technologies LSI53C1020 User Manual
Page 164

IX-4
Index
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
reply free
reply post
,
request post
filter delay
filtering
flash ROM
,
address space
bad signature bit
block diagram
configurations
interface
,
signature recognition
size
,
flexibility
FLSHALE[1:0]/
,
FLSHCE/
,
FRAME/
frames
reply message
request message
,
free running timer
frequency synthesizer
,
function number bit
Fusion-MPT
,
,
,
,
,
,
,
,
,
G
general description
GNT/
,
GPIO[7:0]
,
,
grant
ground signals
H
HB_LED/
,
header type register
host diagnostic register
,
,
host doorbell value
host interface module
,
host interrupt mask register
,
,
host interrupt status register
host system
hot plug
HVD
,
,
sense voltage
hysteresis
I
I/O
base address
base address register
key
processor
,
read command
,
space
supply voltage
write command
,
I/O supply current
ICE
ID control
,
IDC socket
IDD-Core
IDD-I/O
IDDTN
,
IDSEL
,
,
IM
,
in-circuit emulator
information unit
,
input
capacitance
filtering
maximum voltage
reset
signals
INTA/
,
Integrated Mirroring
,
Integrated Striping
integration
interface
EEPROM
external memory
flash ROM
ICE
JTAG
NVSRAM
PCI bus
serial EEPROM
test
interrupt
acknowledge command
ALT_INTA/
coalescing
doorbell mask bit
INTA/