beautypg.com

Avago Technologies LSI53C1020 User Manual

Page 164

background image

IX-4

Index

Version 2.4

Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

reply free

2-7

reply post

2-7

,

4-40

request post

2-7

filter delay

5-8

filtering

5-8

flash ROM

1-3

,

2-5

,

2-23

,

3-12

,

3-13

,

3-20

address space

2-23

bad signature bit

4-36

block diagram

2-25

configurations

2-24

interface

2-23

,

3-12

signature recognition

2-25

,

2-26

size

3-19

,

3-21

flexibility

1-11

FLSHALE[1:0]/

2-25

,

3-13

,

5-6

FLSHCE/

2-25

,

3-12

,

5-6

FRAME/

3-6

,

5-5

frames

reply message

2-7

,

2-15

request message

2-7

,

2-15

free running timer

2-5

frequency synthesizer

3-15

,

3-17

,

3-22

function number bit

4-31

Fusion-MPT

1-3

,

1-5

,

1-9

,

1-10

,

1-11

,

2-1

,

2-3

,

2-4

,

2-6

,

2-7

,

2-8

,

2-26

,

3-12

,

4-1

G

general description

1-1

GNT/

2-15

,

2-28

,

3-6

,

5-6

GPIO[7:0]

2-5

,

3-16

,

3-22

,

5-5

grant

2-15

ground signals

3-16

H

HB_LED/

2-5

,

3-16

header type register

4-9

host diagnostic register

4-35

,

4-36

,

4-39

host doorbell value

4-34

host interface module

2-2

,

2-3

,

2-5

host interrupt mask register

2-15

,

3-7

,

3-8

,

4-40

,

4-41

host interrupt status register

4-40

,

4-41

host system

2-7

hot plug

5-7

HVD

2-22

,

3-9

,

3-10

sense voltage

5-4

hysteresis

5-7

I

I/O

base address

4-5

base address register

2-4

,

2-9

,

4-9

key

4-35

,

4-36

,

4-39

processor

2-4

,

2-28

read command

2-10

,

2-11

,

2-13

space

2-8

,

4-1

,

4-32

supply voltage

5-2

write command

2-10

,

2-11

,

2-13

I/O supply current

5-2

ICE

3-14

ID control

3-19

,

3-20

,

4-14

IDC socket

2-29

IDD-Core

5-2

IDD-I/O

5-2

IDDTN

3-15

,

3-22

,

5-6

IDSEL

2-8

,

2-28

,

3-6

,

3-13

,

5-6

IM

1-4

,

1-12

,

2-5

,

2-23

,

2-26

in-circuit emulator

3-14

information unit

2-18

,

2-20

input

capacitance

5-4

filtering

5-8

maximum voltage

5-2

reset

5-10

signals

5-6

INTA/

2-15

,

3-7

,

4-24

,

4-37

,

4-41

,

5-6

Integrated Mirroring

1-4

,

1-12

,

2-5

,

2-23

,

2-26

Integrated Striping

1-4

integration

1-11

interface

EEPROM

2-27

external memory

2-23

flash ROM

2-23

,

3-12

ICE

3-14

JTAG

3-14

NVSRAM

3-12

PCI bus

3-4

serial EEPROM

2-6

,

2-27

,

3-13

test

3-14

interrupt

2-15

acknowledge command

2-10

,

2-13

ALT_INTA/

2-15

coalescing

1-10

doorbell mask bit

4-41

INTA/

2-15

This manual is related to the following products: