Avago Technologies LSI53C1020 - Manual (Page 167)

Index IX-7
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
memory write block 1-10 , 2-10 , 2-14
special cycle 2-10 , 2-11
split completion 1-10 , 2-10 , 2-13
command register 4-16
configuration read command 2-10 , 2-12 , 2-13 ,
4-6
configuration record 2-27
configuration space 2-8 , 2-27 , 4-1
address map 4-2
C_BE[3:0]/ 2-8 , 2-9
configuration write command 2-10 , 2-12 , 2-13 ,
4-6
DAC 1-10 , 2-8 , 2-10 , 2-13
device complexity bit 4-30
dual address cycles command 2-10 , 2-13
error reporting signals 3-7
frequency synthesizer 3-15 , 3-17 , 3-22
FSN 3-15 , 3-17 , 3-22
functional description 2-8
I/O read command 2-10 , 2-11 , 2-13
I/O space 2-8 , 4-1
I/O space address map 4-32
I/O space and memory space description 4-32
I/O write command 2-10 , 2-11 , 2-13
interface 2-4
interface control signals 3-6
interrupt acknowledge command 2-10 , 2-13
interrupt signals 3-7
Interrupt Status bit 4-7
interrupts 2-15 , 4-41
memory [1] address map 4-33
memory read block command 2-13 , 2-14
memory read command 2-10 , 2-11 , 2-13 , 2-15
memory read dword command 2-11 , 2-13
memory read line command 2-10 , 2-13 , 2-15
memory read multiple command 2-10 , 2-13 ,
2-15
memory space 2-8 , 2-9 , 2-27 , 4-1
memory space [0] 2-4 , 2-9 , 4-1
memory space [1] 2-9 , 4-1
memory write and invalidate command 2-10 ,
2-14 , 2-15
memory write block command 2-12 , 2-14
memory write command 2-10 , 2-14 , 2-15
new capabilities bit 4-6
performance 1-10
power management 2-16
related signals 3-8
reset 4-36
special cycle command 2-10 , 2-11 , 4-5
split completion command 2-13
status 3-20
system address space 4-1
system signals 3-4
PCI_CAP 3-19
PCI_GNT/ 3-13
PCI5VBIAS 1-11 , 3-17 , 5-5
PCI-SIG 4-13
PCI-X 1-10 , 1-11 , 2-8
133 MHz 3-19 , 5-9
133 MHz capable bit 4-30
64-bit device bit 4-30
66 MHz 5-9
alias to memory read block command 2-10
alias to memory write block command 2-10
benefits 1-6
bus number 4-30
capability ID register 4-26
command register 4-27
data parity error recovery enable bit 4-28
designed maximum cumulative read size bit
4-29
designed maximum memory read byte count
bit 4-29
designed maximum outstanding split transac-
tions bit 4-29
device complexity bit 4-30
device number bit 4-31
function number bit 4-31
maximum memory read byte count bits 4-28
maximum outstanding split transactions bits
4-27
memory read block command 2-10
memory read dword command 2-10
memory write block command 2-10
mode 3-19
next pointer register 4-27
received split completion error message bit
4-29
split completion command 2-10
split completion discarded bit 4-30
status 3-20
status register 4-29
unexpected split completion bit 4-30
PERR/ 3-7 , 5-5
pinout 5-22 , 5-24 , 5-27 , 5-29