Avago Technologies LSI53C1020 User Manual
Page 162

IX-2
Index
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
diagnostic write enable
DisARM
doorbell interrupt mask
enable bus mastering
enable I/O
enable memory space
enable parity error response
expansion ROM enable
flash ROM bad signature
function number
interrupt request routing mode
Interrupt Status
IOP doorbell status
MSI enable
multiple message
new capabilities
PME clock
PME enable
PME status
PME support
power management version
power state
received master abort (from master)
received split completion error message
received target abort (from master)
reply interrupt
reply interrupt mask
reset adapter
reset history
SERR/ enable
signalled system error
system doorbell interrupt
TTL interrupt
unexpected split completion
write and invalidate enable
block diagram
board application
boot device
,
boundary scan
burst size selection
bus
mastering
number
PCI commands
training
BZRESET
,
BZVDD
C
C_BE[3:0]/
,
,
C_BE[7:0]/
,
cache line size
,
,
alignment
register
capabilities pointer register
capability ID
MSI
PCI-X
power management
capacitance
input
checksum
class code register
CLK
,
clock
EEPROM
external
PCI
PME
SCLK
,
SCSI
skew control
CLS
CLS alignment
command register
common mode voltage
completer ID
configuration
parameters
read command
,
,
,
record
space
write command
,
,
configuration space
context manager
core voltage
CRC
,
CRC-32
current
I/O supply
latch-up
cyclic redundancy check
D
D0
,