Avago Technologies LSI53C1020 - Manual (Page 106)

4-28 PCI Host Register Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Maximum Memory Read Byte Count [3:2]
These bits indicate the maximum byte count the
LSI53C1020 uses when initiating a sequence with one of
the burst memory read commands. The following table
provides the bit encodings for this field.
Reserved 1
This bit is reserved.
Data Parity Error Recovery Enable 0
The host device driver sets this bit to allow the
LSI53C1020 to attempt to recover from data parity errors.
If the user clears this bit, and the LSI53C1020 is operat-
ing in the PCI-X mode, the LSI53C1020 asserts SERR/
whenever the Master Data Parity Error bit in the PCI
Sta-
tus register is set.
Bits [6:4]
Encoding
Maximum Outstanding
Split Transactions
0b000 1
0b001 2
0b010 3
0b011 4
0b100 8
0b101 Reserved
0b110 Reserved
0b111 Reserved
Bits [3:2]
Encoding
Maximum Memory Read
Byte Count
0b00 512
0b01 1024
0b10 2048
0b11 Reserved