Avago Technologies LSI53C1020 - Manual (Page 158)

A-2 Register Summary
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Expansion ROM Base Address 0x30–0x33 Read/Write 4-15
Capabilities Pointer 0x34 Read Only 4-16
Reserved 0x35–0x37; 0x38–0x3B Reserved 4-16
Interrupt Line 0x3C Read/Write 4-17
Interrupt Pin 0x3D Read Only 4-17
Minimum Grant 0x3E Read Only 4-18
Maximum Latency 0x3F Read Only 4-18
Power Management Capability ID – Read Only 4-19
Power Management Next Pointer – Read Only 4-20
Power Management Capabilities – Read Only 4-20
Power Management Control/Status – Read/Write 4-21
Power Management Bridge Support
Extensions – Read Only 4-22
Power Management Data – Read Only 4-22
MSI Capability ID – Read Only 4-22
MSI Next Pointer – Read Only 4-23
Message Control – Read/Write 4-23
Message Address – Read/Write 4-25
Message Upper Address – Read/Write 4-25
Message Data – Read/Write 4-26
PCI-X Capability ID – Read Only 4-26
PCI-X Next Pointer – Read Only 4-27
PCI-X Command – Read/Write 4-27
PCI-X Status – Read/Write 4-29
1. The offset of the PCI extended capabilities registers can vary. Access these registers through the
Next Pointer and Capability ID registers.
Table A.24 LSI53C1020 PCI Registers (Cont.)
Register Name Offset
1
Read/Write Page