Avago Technologies LSI53C1020 - Manual (Page 10)

x Contents
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Diagnostic Read/Write Address 4-39
Host Interrupt Status 4-40
Host Interrupt Mask 4-41
Request Queue 4-42
Reply Queue 4-42
Chapter 5 Specifications
5.1 DC Characteristics 5-1
5.2 TolerANT Technology Electrical Characteristics 5-7
5.3 AC Characteristics 5-9
5.4 External Memory Timing Diagrams 5-12
5.4.1 NVSRAM Timing 5-12
5.4.2 Flash ROM Timing 5-16
5.5 Pinout Information and Mechanical Drawings 5-20
Appendix A Register Summary
Index
Customer Feedback