Avago Technologies LSI53C1020 - Manual (Page 20)

1-6 Introduction
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
reply messages per interrupt reduces context switching of the host
processor and maximizes the host processor efficiency, which results in
a significant improvement of system performance. To use the interrupt
coalescing feature, the host processor must be able to accept and
manage multiple replies per interrupt.
The Fusion-MPT architecture also provides built-in device driver stability
because the device driver need not change for each revision of the
LSI53C1020 silicon or firmware. This architecture is a reliable, constant
interface between the host device driver and the LSI53C1020. Changes
within the LSI53C1020 are transparent to the host device driver,
operating system, and user. The Fusion-MPT architecture also saves the
user significant development and maintenance effort because it is not
necessary to alter or redevelop the device driver when a revision of the
LSI53C1020 device or firmware occurs.
1.3 Benefits of PCI-X
PCI-X doubles the maximum clock frequency of the conventional PCI
bus. The PCI-X Addendum to the PCI Local Bus Specification,
Revision 1.0a, defines enhancements to the proven PCI Local Bus
Specification, Revision 2.2. PCI-X provides more efficient data transfers
by enabling registered inputs and outputs, improves buffer management
by including transaction information with each data transfer, and reduces
bus overhead by restricting the use of wait states and disconnects. PCI-X
also reduces host processor overhead by providing a wide range of error
recovery implementations.
The LSI53C1020 supports up to a 133 MHz, 64-bit PCI-X bus and is
backward compatible with previous versions of the PCI/PCI-X bus. The
LSI53C1020 includes transaction information with all PCI-X transactions
to enable more efficient buffer management schemes. Each PCI-X
transaction contains a transaction sequence identifier (Tag), the identity
of the initiator, and the number of bytes in the sequence. The
LSI53C1020 clocks PCI-X data directly into and out of registers, which
creates a more efficient data path. The LSI53C1020 increases bus
efficiency because it does not insert wait states after the initial data
phase when acting as a PCI-X target and never inserts wait states when
acting as a PCI-X initiator.