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Table5.17 nvsram write cycle, Nvsram write cycle – Avago Technologies LSI53C1020 User Manual

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5-14

Specifications

Version 2.4

Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Table 5.17

and

Figure 5.9

provide the timing information for NVSRAM

write accesses.

Table 5.17

NVSRAM Write Cycle

Symbol

Parameter

Min

Max

Unit

t

11

Address setup to FLSHALE/ HIGH

25

ns

t

12

Address hold from FLSHALE/ HIGH

25

ns

t

13

FLSHALE/ pulse width

25

ns

t

20

Data setup to RAMWE0/ LOW

40

ns

t

21

Data hold from RAMWE0/ HIGH

30

ns

t

22

RAMWE0/ pulse width

20

ns

t

23

Address setup to RAMWE0/ LOW

75

ns

t

24

RAMCE/ LOW to RAMWE0/ HIGH

60

ns

t

25

RAMCE/ LOW to RAMWE0/ LOW

25

ns

t

26

RAMWE0/ HIGH to RAMCE/ HIGH

25

ns

t

27

RAMCE/ pulse width

100

ns

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