Avago Technologies LSI53C1020 - Manual (Page 68)

3-12 Signal Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
3.5 Memory Interface
Table 3.11 describes the Flash ROM/NVSRAM Interface signals group.
Table 3.11 Flash ROM/NVSRAM Interface Signals
Signal Name
456-Ball
Package 384-Ball
Package
Type Strength Description
MAD[15:0] D22, E21,
B25, D23,
E22, C24,
F22, E23,
D26, E25,
H22, F24,
G23, D25,
F23, G22 C9, B9,
A9, C10,
B10, A10,
C11, D11,
B14, A14,
A13, B13,
A12, B12,
D12, C12 I/O 8 mA The Memory Address and Data Bus
carries the memory and address signals
for the Flash ROM and NVSRAM
interfaces on MAD[7:0]. These pins also
provide the Power-On Sense options
that configure operating parameters
during chip power-up or reset.
MADP[1:0] C22, B24 A8, D9 I/O 8 mA The Memory Address and Data Parity
signals provide parity checking for
MAD[15:0]. By default, the LSI53C1020
uses even parity. The user can enable
odd parity through the Fusion-MPT
architecture.
These pins also provide the Power-On
Sense options that configure operating
parameters during chip power-up or
reset.
RAMOE/ G26 D15 O 4 mA The LSI53C1020 asserts active LOW
Memory Output Enable to indicate that
the selected NVSRAM or Flash ROM
device can drive data. This signal is
typically an asynchronous input to
NVSRAM and/or Flash ROM devices.
RAMWE[1:0]/ E24, H23 A11, A15 O 8 mA The LSI53C1020 asserts active LOW
Memory Byte Write Enables to allow
single byte writes to the NVSRAM.
RAMWE0/ enables writes on MAD[7:0].
RAMCE/ D20 A7 O 8 mA When MAD[3] is pulled HIGH, the
LSI53C1020 asserts active LOW
synchronous RAM Chip Enable to
select the NVSRAM.
FLSHCE/ G25 B15 O 8 mA The LSI53C1020 asserts active LOW
Flash Chip Enable to enable data
transfers with a single 8-bit device.