Avago Technologies LSI53C1020 - Manual (Page 49)

External Memory Interfaces 2-23
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
2.4.2.2 SCSI Termination
The terminator networks pull signals to an inactive voltage level and
match the impedance seen at the end of the cable to the characteristic
impedance of the cable. Install terminators at the extreme ends of the
SCSI chain, and only at the ends; all SCSI buses must have exactly two
terminators.
Note: If using the LSI53C1020 in a design with an 8-bit SCSI bus,
designers must terminate all 16 data lines.
2.5 External Memory Interfaces
The LSI53C1020 provides Flash ROM, NVSRAM, and serial EEPROM
interfaces. The Flash ROM interface stores the SCSI BIOS and firmware
image. The Flash ROM is optional if the LSI53C1020 is not the boot
device and a suitable driver exists to initialize the LSI53C1020. Integrated
Mirroring (IM) technology requires an NVSRAM for write journaling. The
nonvolatile external serial EEPROM stores configuration parameters for
the LSI53C1020.
2.5.1 Flash ROM Interface
The Flash ROM interface multiplexes the 8-bit address and data buses
on the MAD[7:0] pins. The interface latches the address into three 8-bit
latches to support up to 1 Mbyte of address space. The interface
supports byte, word, and dword accesses. The LSI53C1020 dword aligns
dword reads, word aligns word reads, and byte aligns byte reads. The
remaining bits from word and byte reads are meaningless.
The MAD[2:1] Power-On Sense pin configurations define the size of the
Flash ROM address space.
Table 2.3 provides the pin encoding for these