Avago Technologies LSI53C1020 User Manual
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PCI Host Register Description
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
0b10 in this field to indicate that the designed maximum
memory read bytes count is 2048.
Device Complexity
20
The PCI function clears this read-only bit to indicate that
the LSI53C1020 is a simple device.
Unexpected Split Completion
19
The PCI function sets this read-only bit when it receives
an unexpected split completion. When set, this bit
remains set until software clears it. Write a one (1) to this
bit to clear it.
Split Completion Discarded
18
The PCI function sets this read-only bit when it discards
a split completion. When set, this bit remains set until
software clears it. Write a one (1) to this bit to clear it.
133 MHz Capable
17
The MAD[15] Power-On Sense pin controls this read-only
bit. Allowing the internal pull-downs to pull MAD[15] LOW
sets this bit and enables 133 MHz operation of the PCI
bus. Pulling MAD[15] HIGH clears this bit and disables
133 MHz operation of the PCI bus. Refer to
“Power-On Sense Pins Description,” page 3-18
, for more
information concerning the Power-On Sense pins.
64-bit Device
16
The MAD[14] Power-On Sense pin controls this read-only
bit. Allowing the internal pull-downs to pull MAD[14] LOW
sets this bit and indicates a 64-bit PCI Address/Data bus.
Pulling MAD[14] HIGH clears this bit and indicates a
32-bit PCI Address/Data bus. If using the LSI53C1020 on
an add-in card, this bit must indicate the size of the PCI
Address/Data bus on the card. Refer to
“Power-On Sense Pins Description,” page 3-18
for more
information concerning the Power-On Sense pins.
Bus Number
[15:8]
These read-only bits indicate the number of the
LSI53C1020 bus segment. This PCI function uses this
number as part of its Requester ID and Completer ID.
This field is read for diagnostic purposes only.