Minimum grant, Maximum latency, Register: 0x3e – Avago Technologies LSI53C1020 User Manual
Page 96: Register: 0x3f
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PCI Host Register Description
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Register: 0x3E
Minimum Grant
Read Only
Min_Gnt
[7:0]
This 8-bit register specifies the desired settings for the
latency timer values in units of 0.25
µ
s. This register
specifies how long of a burst period the device needs.
The LSI53C1020 sets this register to 0x10, indicating a
burst period of 4.0
µ
s.
Register: 0x3F
Maximum Latency
Read Only
Max_Lat
[7:0]
This 8-bit register specifies the desired settings for the
latency timer values in units of 0.25
µ
s. This register
specifies how often the device needs to gain access to
the PCI bus. The LSI53C1020 SCSI function sets this
register to 0x06 because it requires the PCI bus every
1.5
µ
s to maintain a data transfer rate of 320 Mbytes/s.
7
0
Minimum Grant
0
0
0
1
0
0
0
0
7
0
Maximum Latency
0
0
0
0
0
1
1
0