Avago Technologies LSI53C1020 - Manual (Page 82)

4-4 PCI Host Register Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Reserved [15:11]
This field is reserved.
Interrupt Disable 10
Setting this bit disables the LSI53C1020A from asserting
the interrupt signal. Clearing this bit enables the assertion
of its interrupt signal. This bit’s state after RST/ is 0.
(Interrupt Disable is supported only by the LSI53C1020A
controller.)
Reserved 9
This bit is reserved.
SERR/ Enable 8
Setting this bit enables the LSI53C1020 to activate the
SERR/ driver. Clearing this bit disables the SERR/ driver.
Reserved 7
This bit is reserved.
Enable Parity Error Response 6
Setting this bit enables the LSI53C1020 PCI function to
detect parity errors on the PCI bus and report these
errors to the system. Clearing this bit causes the
LSI53C1020 PCI function to set the Detected Parity Error
bit, bit 15 in the PCI
Status register, but not to assert
PERR/ when the PCI function detects a parity error. This
bit only affects parity checking. The PCI function always
generates parity for the PCI bus.
Reserved 5
This bit is reserved.
Write and Invalidate Enable 4
Setting this bit enables the PCI function to generate write
and invalidate commands on the PCI bus when operating
in the conventional PCI mode.
Reserved 3
This bit is reserved.
Enable Bus Mastering 2
Setting this bit allows the PCI function to behave as a PCI
bus master. Clearing this bit disables the PCI function
from generating PCI bus master accesses.