Avago Technologies LSI53C1020 - Manual (Page 35)

PCI Functional Description 2-9
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
I/O Base Address register determines the 256-byte PCI I/O area that the
PCI device occupies.
2.3.1.3 PCI Memory Space
The LSI53C1020 contains two PCI memory spaces: PCI Memory
Space [0] and PCI Memory Space [1]. PCI Memory Space [0] supports
normal memory accesses, while PCI Memory Space [1] supports
diagnostic memory accesses. The LSI53C1020 requires 64 Kbytes of
memory space.
The PCI specification defines memory space as a contiguous, 64-bit
memory address that all system resources share. The
Memory [0] Low
and Memory [0] High registers determine which 64 Kbyte memory area
PCI Memory Space [0] occupies. The Memory [1] Low and Memory [1]
High registers determine which 64 Kbyte memory area PCI Memory
Space [1] occupies.
2.3.2 PCI Commands and Functions
Bus commands indicate to the target the type of transaction the master
is requesting. The master encodes the bus commands on the C_BE[3:0]/
lines during the address phase. The PCI bus command encodings
appear in
Table 2.1 .