Avago Technologies LSI53C1020 - Manual (Page 11)

Contents xi
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Figures
1.1 Typical LSI53C1020 Board Application 1-3
1.2 Typical LSI53C1020 System Application 1-4
2.1 LSI53C1020 Block Diagram 2-3
2.2 Paced Transfer Example 2-19
2.3 Example of Precompensation 2-20
2.4 Flash ROM Block Diagram 2-25
2.5 NVSRAM Diagram 2-26
2.6 ZCR Circuit Diagram for the LSI53C1020 and
LSI53C1000R
2-29
3.1 LSI53C1020/1020A Functional Signal Grouping 3-3
5.1 LVD Driver 5-3
5.2 LVD Receiver 5-4
5.3 Rise and Fall Time Test Condition 5-8
5.4 SCSI Input Filtering 5-8
5.5 External Clock 5-9
5.6 Reset Input 5-10
5.7 Interrupt Output 5-11
5.8 NVSRAM Read Cycle 5-13
5.9 NVSRAM Write Cycle 5-15
5.10 Flash ROM Read Cycle 5-17
5.11 Flash ROM Write Cycle 5-19
5.12 LSI53C1020 456-Pin BGA Top View 5-21
5.13 LSI53C1020A 384-Pin BGA, Top View 5-26
5.14 456-Pin EPBGA (KY) Mechanical Drawing 5-31
5.15 384-Ball Count EPBGA (HT) Mechanical Drawing
(Sheet 1 of 2)
5-32
5.16 448-Ball Count EPBGA (5B) Mechanical Drawing
(Sheet 1 of 2)
5-34