Avago Technologies LSI53C1020 - Manual (Page 14)

xiv Contents
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
5.3 LVD Driver SCSI Signals – SACK
±
, SATN
±
, SBSY
±
,
SCD
±
, SD[15:0]
±
, SDP[1:0]
±
, SIO
±
, SMSG
±
, SREQ
±
,
SRST
±
, SSEL
±
5-3
5.4 LVD Receiver SCSI Signals – SACK
±
, SATN
±
, SBSY
±
,
SCD
±
, SD[15:0]
±
, SDP[1:0]
±
, SIO
±
, SMSG
±
, SREQ
±
,
SRST
±
, SSEL
±
5-4
5.5 DIFFSENS SCSI Signal 5-4
5.6 Input Capacitance 5-4
5.7 8 mA Bidirectional Signals – GPIO[7:0], MAD[15:0],
MADP[1:0], SerialDATA
5-5
5.8 8 mA PCI Bidirectional Signals – ACK64/, AD[63:0],
C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, PAR, PAR64,
PERR/, REQ64/, SERR/, STOP/, TRDY/
5-5
5.9 Input Signals – CLK, DIS_PCI_FSN/, DIS_SCSI_FSN/,
GNT/, IDDTN, IDSEL, IOPD_GNT, BZRESET, BZVDD,
JtagMode, SCANEN, SCAN_MODE, SCLK, TCK_CHIP,
TCK_ICE, TESTACLK, TM, TESTHCLK, TDI_CHIP,
TDI_ICE, TMS_CHIP, TMS_ICE, TN, TRST_ICE/,
TST_RST/, ZCR_EN/
5-6
5.10 8 mA Output Signals – ALT_INTA/, RAMWE[1:0]/,
FLSHALE[1:0]/, FLSHCE/, INTA/, RAMOE/, RAMCE/,
REQ/, RTCK_ICE, SerialCLK, TDO_CHIP, TDO_ICE
5-6
5.11 12 mA Output Signals – A_LED/, HB_LED/ 5-6
5.12 TolerANT Technology Electrical Characteristics for
SE SCSI Signals
5-7
5.13 External Clock 5-9
5.14 Reset Input 5-10
5.15 Interrupt Output 5-11
5.16 NVSRAM Read Cycle Timing 5-12
5.17 NVSRAM Write Cycle 5-14
5.18 Flash ROM Read Cycle Timing 5-16
5.19 Flash ROM Write Cycle 5-18
5.20 LSI53C1020 456-Pin Pinout by Signal Name 5-22
5.21 LSI53C1020 456-Pin Pinout by BGA Position 5-24
5.22 LSI53C1020A 384-Pin Pinout by Signal Name 5-27
5.23 LSI53C1020A 384-Pin Pinout by BGA Position 5-29
A.24 LSI53C1020 PCI Registers A-1
A.25 LSI53C1020 PCI I/O Space Registers A-3
A.26 LSI53C1020 PCI Memory [0] Registers A-4