Avago Technologies LSI53C1020 - Manual (Page 69)

Zero Channel RAID (ZCR) Interface 3-13
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Table 3.12 describes the serial EEPROM Interface signals group.
3.6 Zero Channel RAID (ZCR) Interface
Table 3.13 describes the ZCR configuration signals group.
FLSHALE[1:0]/ J24, K22 B16, A16 O 8 mA The Flash ROM and NVSRAM interfaces
use active LOW Flash Address Latch
Enable. For the Flash ROM, these
signals provide clocks for address
latches. For the NVSRAM, they provide
the memory address strobe.
Table 3.11 Flash ROM/NVSRAM Interface Signals (Cont.)
Signal Name
456-Ball
Package 384-Ball
Package
Type Strength Description
Table 3.12 Serial EEPROM Interface Signals
Signal Name
456-Ball
Package 384-Ball
Package
Type Strength Description
SerialCLK J25 B17 O 8 mA Serial EEPROM clock. This signal
requires a 4.7 k
Ω
external pull-up
resistor when an EEPROM is present.
SerialDATA H26 C17 I/O 8 mA Serial EEPROM data. This signal
requires a 4.7 k
Ω
external pull-up
resistor when an EEPROM is present.
Table 3.13 ZCR Configuration Signals
Signal Name
456-Ball
Package 384-Ball
Package
Type Strength Description
ZCR_EN/ N23 G24 I N/A Enables and disables ZCR support on the
LSI53C1020. By default, this signal is
internally pulled HIGH to disable ZCR
operation. Pull this signal LOW to enable
ZCR operation.
IOPD_GNT AC5 AD4 I N/A When ZCR is enabled on the LSI53C1020,
the device only responds to PCI
configuration cycles if IOPD_GNT or IDSEL
is asserted. Connect IOPD_GNT to
PCI_GNT/ on the external I/O processor.