Avago Technologies LSI53C1020 User Manual
Page 84
4-6
PCI Host Register Description
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Received Target Abort (from Master)
12
A master device sets this bit when a Target Abort com-
mand terminates its transaction.
Reserved
11
This bit is reserved.
DEVSEL/ Timing
[10:9]
These two read-only bits encode the timing of DEVSEL/
and indicate the slowest time that a device asserts
DEVSEL/ for any bus command except Configuration
Read and Configuration Write. The LSI53C1020 only
supports medium DEVSEL/ timing. The possible timing
values are as follows:
Data Parity Error Reported
8
This bit is set according to the PCI Local Bus Specifica-
tion, Revision 2.2, and PCI-X Addendum to the PCI Local
Bus Specification, Revision 1.0a. Refer to bit 0 of the
register for more information.
Reserved
[7:6]
This field is reserved.
66 MHz Capable
5
The MAD[13] Power-On Sense pin controls this bit.
Allowing the internal pull-down to pull MAD[13] LOW sets
this bit and indicates to the host system that the
LSI53C1020 PCI function is capable of operating at
66 MHz. Pulling MAD[13] HIGH clears this bit and indi-
cates to the host system that the LSI53C1020 PCI func-
tion is not configured to operate at 66 MHz. Refer to
Section 3.10, “Power-On Sense Pins Description,”
page 3-18
, for more information.
New Capabilities
4
The LSI53C1020 PCI function sets this read-only bit to
indicate a list of PCI extended capabilities such as PCI
Power Management, MSI, and PCI-X support.
0b00
Fast
0b01
Medium
0b10
Slow
0b11
Reserved