Avago Technologies LSI53C1020 - Manual (Page 43)

PCI Functional Description 2-17
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
A function in Power State D1 places the SCSI core in the snooze mode.
In the snooze mode, a SCSI reset does not generate an IRQ/ signal.
2.3.6.3 Power State D2
According to the PCI Power Management Interface Specification, Power
State D2 must have a power level equal to or lower than Power State D1.
A function in this state places the SCSI core in the coma mode. Placing
the PCI Function in Power State D2 disables the SCSI and DMA
interrupts, and suppresses the following PCI Configuration Space
Command register enable bits:
•
I/O Space Enable
•
Memory Space Enable
•
Bus Mastering Enable
•
SERR/Enable
•
Enable Parity Error Response
Therefore, the memory and I/O spaces in a function cannot be accessed,
and the PCI function cannot be a PCI bus master.
If the PCI function is changed from Power State D2 to Power State D1
or Power State D0, the PCI function restores the previous values of the
PCI
Command register and asserts any interrupts that were pending
before the function entered Power State D2.
2.3.6.4 Power State D3
According to the PCI Power Management Interface Specification, Power
State D3 must have a power level equal to or lower than Power State D2.
Power State D3 is the minimum power state and includes the D3
hot
and
D3
cold
settings. D3
hot
allows the device to transition to D0 using software.
D3
cold
removes power from the LSI53C1020. D3
cold
can transition to D0
by applying VCC and resetting the device.
Placing a function in Power State D3 puts the LSI53C1020 core in the
coma mode, clears the PCI
Command register, and continually asserts
the function's soft reset. Asserting soft reset clears all pending interrupts
and 3-states the SCSI bus.