Avago Technologies LSI53C1020 User Manual
Page 165
Index
IX-5
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
line register
message signalled
MSI
output
PCI
pin register
pins
reply
reply bit
reply mask bit
request routing mode bits
service routine
system doorbell
,
system doorbell bit
TTL bit
Interrupt Status bit
intersymbol interference
,
IOP
,
,
,
,
boot
IOP doorbell status bit
IOPD_GNT
,
IRDY/
,
IS
ISI
,
ISR
IU_Request
J
JTAG
,
JtagMode
junction temperature
K
key
I/O
,
L
latch-up current
latch-up protection
latency timer
latency timer register
lead temperature
LED
low voltage differential
LSI53C1000R
,
LVD
,
,
driver SCSI signals
receiver SCSI signals
receiver voltage
sense voltage
LVDlink
,
,
M
MAD[10]
MAD[13]
MAD[14]
MAD[15:0]
,
MAD[15]
MAD[2:1]
MAD[3]
MAD[7:0]
,
,
MAD[7]
MADP[0]
MADP[1:0]
,
,
margin control settings
master abort
master data parity error
max_lat
maximum latency register
maximum memory read byte count bits
maximum outstanding split transactions bits
maximum stress ratings
MCS
mechanical drawing
memory
alias to read block
alias to write block
,
controller
flash ROM size
read block command
,
read command
,
read dword command
,
,
read line command
,
read multiple command
,
space
write and invalidate command
,
,
write block command
,
,
write command
,
,
memory [0] high
memory [0] low
,
memory [1] high
memory [1] low
,