Avago Technologies LSI53C1020 - Manual (Page 85)

PCI Configuration Space Register Descriptions 4-7
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Interrupt Status 3
This read-only bit reflects the state of the interrupt in the
LSI53C1020A. The interrupt signal is asserted only when
the Interrupt Disable bit in the command register is
cleared and this Interrupt Status bit is set. (Interrupt Sta-
tus is supported only by the LSI53C1020A controller.)
Reserved [2:0]
This field is reserved.
Register: 0x08
Revision ID
Read/Write
Revision ID [7:0]
This 8-bit register indicates the current revision level of
the device.
Register: 0x09–0x0B
Class Code
Read Only
Class Code [23:0]
This 24-bit register identifies the generic function of the
device. The upper byte of this register is a base class
code, the middle byte is a subclass code, and the lower
byte identifies a specific register-level programming inter-
face. The value of this register is 0x010000, which iden-
tifies a SCSI controller.
7 0
Revision ID
X X X X X X X X
23 0
Class Code
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0