Avago Technologies LSI53C1020 - Manual (Page 170)

IX-10 Index
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
termination 2-23
TolerANT technology 1-8
Ultra320 features 2-18
SD[15:0]+- 3-9 , 5-3 , 5-4
SDP[1:0]+- 3-9 , 5-3 , 5-4
SE 2-22 , 3-9 , 3-10
sense voltage 5-4
sense voltage 5-4
serial EEPROM 2-5 , 2-6 , 2-23 , 2-27 , 3-20 , 3-22 ,
4-13 , 4-14 , 4-37
configuration record 2-27
download enable 3-19 , 3-20
interface 2-27
SerialCLK 3-13 , 3-22
SerialDATA 3-13 , 3-22 , 5-5
SERR/ 3-7 , 4-28 , 5-5 , 5-6
SERR/ enable bit 4-4
shared RAM 2-5 , 2-7
signal
grouping 3-3
list 5-22 , 5-24 , 5-27 , 5-29
no connect 3-1
types 3-2
signal descriptions
A_LED 3-16
ACK64/ 3-6
AD[63:0] 3-5
ALT_INTA/ 3-8
BZRESET 3-8
BZVDD 3-8
C_BE[7:0]/ 3-5
CLK 3-4
DEVSEL/ 3-6
DIFFSENSE 3-10
DIS_PCI_FSN/ 3-15
DIS_SCSI_FSN/ 3-15
FLSHALE[1:0]/ 3-13
FLSHCE/ 3-12
FRAME/ 3-6
GNT/ 3-6
GPIO[7:0] 3-16
ground 3-16
HB_LED/ 3-16
IDDTN 3-15
IDSEL 3-6
INTA/ 3-7
IOPD_GNT 3-13
IRDY/ 3-6
JtagMode 3-15 , 3-22
MAD[15:0] 3-12 , 3-18
MADP[1:0] 3-12 , 3-18
NC 3-18
PAR 3-5
PAR64 3-5
PCI5VBIAS 3-17
PERR/ 3-7
power 3-16
power-on sense 3-18
RAMCE/ 3-12
RAMOE/ 3-12
RAMWE[1:0]/ 3-12
RBIAS 3-10
REQ/ 3-6
REQ64/ 3-6
RST/ 3-4
RTCK_ICE 3-14
SACK+- 3-11
SATN+- 3-11
SBSY+- 3-11
SCAN_MODE 3-15
SCANEN 3-15
ScanRstDis 3-15
SCD+- 3-11
SCLK 3-9
SD[15:0]+- 3-9
SDP[1:0]+- 3-9
SerialCLK 3-13
SerialDATA 3-13
SERR/ 3-7
SIO+- 3-11
SMSG+- 3-11
SPARE[13:12] 3-15
SREQ+- 3-11
SRST+- 3-11
SSEL+- 3-11
STOP/ 3-6
TCK_CHIP 3-14
TCK_ICE 3-14
TDI_CHIP 3-14
TDI_ICE 3-14
TDO_CHIP 3-14
TDO_ICE 3-14
TESTACLK 3-15
TESTHCLK 3-15
TM 3-15
TMS_CHIP 3-14