Avago Technologies LSI53C1020 - Manual (Page 27)

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual 2-1
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Chapter 2
Functional Description
This chapter provides a subsytem level overview of the LSI53C1020, a
discussion of the Fusion-MPT architecture, and a functional description
of the LSI53C1020 interfaces. This chapter contains the following
sections:
•
Section 2.1, “Block Diagram Description”
•
Section 2.2, “Fusion-MPT Architecture Overview”
•
Section 2.3, “PCI Functional Description”
•
Section 2.4, “Ultra320 SCSI Functional Description”
•
Section 2.5, “External Memory Interfaces”
•
Section 2.6, “Serial EEPROM Interface”
•
Section 2.7, “Zero Channel RAID”
•
Section 2.8, “Multi-ICE Test Interface”
The LSI53C1020 is a high-performance, intelligent PCI-X to Ultra320
SCSI Controller. The LSI53C1020 controller supports the PCI Local Bus
Specification, Revision 2.2; the LSI53C1020A controller supports
Revision 2.3 of this spec. Both controllers support the PCI-X Addendum
to the PCI Local Bus Specification, Revision 1.0a and the proposed SCSI
Parallel Interface-4 (SPI-4) draft standard.
Note: In the rest of this chapter, LSI53C1020 refers to both the
LSI53C1020 SCSI controller and the LSI53C1020A SCSI
controller, unless specifically noted.
The LSI53C1020 employs the Fusion-MPT architecture to ensure robust
system performance, to support binary compatibility of host software
between the LSI Logic SCSI and Fibre Channel products, and to
significantly reduce software development time. Refer to the Fusion-MPT
Device Management User’s Guide for more information on the