Avago Technologies LSI53C1020 - Manual (Page 172)

IX-12 Index
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
TESTACLK 3-15 , 3-22 , 5-6
TESTHCLK 3-15 , 3-22 , 5-6
TestReset/ 4-36
thermal resistance 5-2
timer 2-5
timing
external memory 5-11
interrupt output 5-11
PCI and PCI-X 5-9
power-up 5-11
reset 5-10
timing diagrams 5-11
Tj 5-2
TM 3-15 , 3-22 , 5-6
TMS_CHIP 3-14 , 3-22 , 5-6
TMS_ICE 2-30 , 3-14 , 3-22 , 5-6
TN 3-15 , 3-22 , 5-6
TolerANT 1-8 , 1-12 , 5-7
transfer period 2-18
transfer width 2-18
transfers
information units 2-20
packetized 2-20
TRDY/ 3-6 , 5-5
TRST_ICE/ 2-30 , 3-14 , 3-22 , 5-6
TST_RST/ 3-14 , 3-22 , 5-6
TTL interrupt bit 4-37
U
Ultra160 SCSI
DT clocking 1-2 , 2-18
parallel protocol request 2-21
PPR 2-21
Ultra320 SCSI 1-5 , 1-7
benefits 1-7
bus training 1-9
channel module 2-2
core 2-6
CRC 2-21
domain validation 2-22
DT clocking 1-2 , 2-18
features 1-2 , 2-18
functional description 2-18
information unit 2-20
ISI 1-7 , 2-18
paced transfers 2-18
packetized transfers 2-20
parallel protocol request 2-18 , 2-21
PPR 2-18
precompensation 2-20
QAS 2-21
quick arbitration and selection 2-21
skew compensation 1-2 , 1-7 , 1-9 , 2-21
unexpected split completion bit 4-30
V
VDD_CORE 5-2
VDD_IO 3-16 , 5-2
VDDA 3-17
VDDBIAS 3-9
VDDC 3-17
vendor ID register 4-3
version bit 4-20
voltage
analog 5-2
common mode 5-3
core 5-2
feed-through protection 1-12
I/O 5-2
input maximum 5-2
supply 5-2
VSS_IO 3-17
VSSA 3-17
VSSC 3-17
W
write and invalidate enable bit 4-4
write flow 2-18
write I/O key 4-35 , 4-36 , 4-39
write journaling 2-26
write sequence register 4-35 , 4-36 , 4-39
Z
ZCR 2-28 , 2-29 , 3-13
ZCR_EN/ 2-28 , 3-13 , 3-22 , 5-6
zero channel RAID 2-28 , 2-29 , 3-13