Avago Technologies LSI53C1020 - Manual (Page 30)

2-4 Functional Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
2.1.1.1 PCI Interface
The LSI53C1020 provides a PCI-X interface that supports up to a 64-bit,
133 MHz PCI-X bus. The interface is compatible with all previous
implementations of the PCI specification. For more information on the
PCI interface, refer to
Section 2.3, “PCI Functional Description,”
page 2-8 .
2.1.1.2 System Interface
The system interface efficiently passes messages between the
LSI53C1020 and other I/O agents using a high-performance, packetized,
mailbox architecture. The LSI53C1020 system interface coalesces PCI
interrupts to minimize traffic on the PCI bus and maximize system
performance.
All host accesses to the IOP, external memory, and timer and
configuration subsystems pass through the system interface and use the
primary bus. The host system initiates data transactions on the primary
bus with the system interface registers. PCI Memory Space [0] and the
PCI I/O Base Address registers identify the location of the system
interface register set.
Chapter 4, “PCI Host Register Description,”
provides a bit-level description of the system interface register set.
2.1.1.3 I/O Processor (IOP)
The LSI53C1020 I/O processor (IOP) is a 32-bit ARM966E-S RISC
processor. The IOP controls the system interface and uses the
Fusion-MPT architecture to manage the host side of non-DMA accesses
to the Ultra320 SCSI bus. The context manager uses the Fusion-MPT
architecture to control the SCSI side of data transfers. The IOP and
Context Manager completely manage all SCSI I/Os without host
intervention. Refer to
Section 2.2, “Fusion-MPT Architecture Overview,”
page 2-7 , for more information on the Fusion-MPT architecture.
2.1.1.4 DMA Arbiter and Router
The descriptor-based DMA Arbiter and Router subsystem manages the
transfer of memory blocks between local memory and the host system.
The DMA channel includes PCI bus master interface logic, the internal
bus interface logic, and a 256-byte system DMA FIFO.