Avago Technologies LSI53C1020 - Manual (Page 150)

5-30 Specifications
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Table 5.23 LSI53C1020A 384-Pin Pinout by BGA Position (Cont.)
Ball Signal
U2 SD3-
U3 SD2+
U4 VDD_IO
U23 VDD_IO
U24 VDDC
U25 PCI5VBIAS
U26 NC
V1 SD2-
V2 SD1+
V3 SD0+
V4 SD1-
V23 AD1
V24 AD0
V25 ACK64/
V26 REQ64/
W1 SD0-
W2 SDP1+
W3 SD15+
W4 SDP1-
W23 AD5
W24 AD4
W25 AD3
W26 AD2
Y1 SD15-
Y2 SD14+
Y3 SD13+
Y4 SD14-
Y23 AD8
Y24 C_BE0/
Y25 AD7
Y26 AD6
AA1 SD13-
AA2 SD12+
AA3 NC
AA4 SD12-
AA23 VDD_IO
AA24 AD11
AA25 AD10
AA26 AD9
AB1 NC
AB2 NC
AB3 NC
AB4 VDD_IO
AB23 VSS_IO
AB24 VDDA
AB25 CLK
AB26 AD12
AC1 NC
AC2 NC
AC3 NC
AC4 VSS_IO
AC5 VSS_IO
AC6 VDD_IO
AC7 DIS_SCSI_FSN/
AC8 TST_RST/
AC9 VDDC
AC10 VDD_IO
AC11 PCI5VBIAS
AC12 PCI5VBIAS
AC13 VDD_IO
AC14 VDD_IO
AC15 AD24
AC16 AD22
AC17 VDD_IO
AC18 VSSC
AC19 FRAME/
AC20 STOP/
AC21 C_BE1/
AC22 VDD_IO
AC23 VSS_IO
AC24 NC
AC25 NC
AC26 VSSA
AD1 NC
AD2 NC
AD3 VSS_IO
AD4 IOPD_GNT
AD5 TDI_ICE
AD6 RTCK_ICE
AD7 TESTHCLK
AD8 VSSC
AD9 TDI_CHIP
AD10 TDO_CHIP
AD11 BZVDD
AD12 RST/
AD13 AD31
AD14 AD27
AD15 C_BE3/
AD16 AD21
AD17 VDDC
AD18 AD17
AD19 IRDY/
AD20 PERR/
AD21 AD15
AD22 NC
AD23 NC
AD24 VSS_IO
AD25 NC
AD26 NC
AE1 NC
AE2 VSS_IO
AE3 NC
AE4 TCK_ICE
AE5 TDO_ICE
AE6 VDDC
AE7 TESTACLK
AE8 TCK_CHIP
AE9 ScanRstDis
AE10 VSSC
AE11 INTA/
AE12 GNT/
AE13 AD30
AE14 AD28
AE15 AD25
AE16 AD23
AE17 PCI5VBIAS
AE18
AD18
AE19 C_BE2/
AE20 DEVSEL/
AE21 PAR
AE22 AD13
AE23 NC
AE24 NC
AE25 VSS_IO
AE26 NC
AF2 NC
AF3 IDDTN
AF4 TMS_ICE
AF5 TRST_ICE/
AF6 VSSC
AF7 VDDC
AF8 TMS_CHIP
AF9 NC
AF10 BZRESET
AF11 ALT_INTA/
AF12 REQ/
AF13 PCI5VBIAS
AF14
AD29
AF15 AD26
AF16 IDSEL
AF17 AD20
AF18 AD19
AF19 AD16
AF20 TRDY/
AF21 SERR/
AF22 AD14
AF23 PCI5VBIAS
AF24
NC
AF25 NC
Ball Signal Ball Signal Ball Signal