Avago Technologies LSI53C1020 - Manual (Page 24)

1-10 Introduction
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
1.8.2 PCI Performance
The LSI53C1020 supports the following PCI features:
• Has a 133 MHz, 64-bit PCI/PCI-X interface that:
– Operates at 33 MHz or 66 MHz PCI
– Operates at up to 133 MHz PCI-X
– Supports 32-bit or 64-bit data
– Supports 32-bit or 64-bit addressing through Dual Address Cycles
(DACs)
– Provides a theoretical 1066 Mbytes/s zero wait state transfer rate
– Complies with PCI Local Bus Specification, Revision 2.2
(LSI53C1020) or Revision 2.3 (LSI53C1020A)
– Complies with the PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0a
– Complies with the PCI Power Management Interface
Specification, Revision 1.1
– Complies with the PC2001 System Design Guide
• Offers unmatched performance through the Fusion-MPT architecture
• Provides high throughput and low CPU utilization to offload the host
processor
• Uses SCSI Interrupt Steering Logic (SISL) to provide alternate
interrupt routing for RAID applications
• Reduces Interrupt Service Routine (ISR) overhead with interrupt
coalescing
• Supports 32-bit or 64-bit data bursts with variable burst lengths
• Supports the PCI Cache Line Size register
• Supports the PCI Memory Write and Invalidate, Memory Read Line,
and Memory Read Multiple commands
• Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, and Memory Write Block commands
• Supports up to eight PCI-X outstanding split transactions
• Supports Message Signaled Interrupts (MSIs)