Avago Technologies LSI53C1020 - Manual (Page 110)

4-32 PCI Host Register Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
4.2 I/O Space and Memory Space Register Descriptions
This section describes the host interface registers in the PCI I/O Space
and PCI Memory Space. These address spaces contain the Fusion-MPT
interface register set. PCI Memory Space [0] and PCI Memory Space [1]
form the PCI Memory Space. PCI Memory [0] supports normal memory
accesses while PCI Memory Space [1] supports diagnostic memory
accesses. For all registers except the
Diagnostic Read/Write Data and
Diagnostic Read/Write Address registers, access the address offset
through either PCI I/O Space or PCI Memory Space [0]. Access to the
Diagnostic Read/Write Data and Diagnostic Read/Write Address
registers is only through PCI I/O Space.
Table 4.3 defines the PCI I/O Space address map.
Table 4.3 PCI I/O Space Address Map
31 0 Offset Page
System Doorbell 0x0000 4-34
Write Sequence 0x0004 4-35
Host Diagnostic 0x0008 4-36
Test Base Address 0x000C 4-37
Diagnostic Read/Write Data 0x0010 4-38
Diagnostic Read/Write Address 0x0014 4-39
Reserved 0x0018–0x002F –
Host Interrupt Status 0x0030 4-40
Host Interrupt Mask 0x0034 4-41
Reserved 0x0038–0x003F –
Request Queue 0x0040 4-42
Reply Queue 0x0044 4-42
Reserved 0x0048–0x007F –