Avago Technologies LSI53C1020 - Manual (Page 168)

IX-8 Index
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
PME 4-20 , 4-21
clock bit 4-20
enable bit 4-21
status bit 4-21
support bits 4-20
POR 4-36
POST 4-17
power management 2-16
aux_current bit 4-20
bridge support extensions register 4-22
capabilities register 4-20
capability ID register 4-19
control/status 2-16
control/status register 2-16 , 4-21
D0 4-21
D1 4-21
D1 support bit 4-20
D2 4-21
D2 support bit 4-20
D3 2-17 , 4-21
data register 4-22
data scale bit 4-21
data select bit 4-21
device specific initialization bit 4-20
event 4-20
interface 1-10
next pointer register 4-19
PME clock bit 4-20
PME enable bit 4-21
PME status bit 4-21
power state bit 4-21
support bits 4-20
version bit 4-20
power signals 3-16
power state
D0 2-16
D1 2-16
D2 2-16 , 2-17
D3 2-16 , 2-17 , 4-21
power state bit 4-21
power-on reset 4-36
power-on sense pins 3-18
PPR 2-18 , 2-19 , 2-21
precompensation 1-2 , 2-18 , 2-20
pull-ups and pull-downs 3-22
Q
QAS 1-2 , 1-9 , 2-18 , 2-21
queue
message 2-7
reply message 2-5 , 2-7
request message 2-5 , 2-7
quick arbitration and selection 1-2 , 1-9 , 2-18 , 2-21
R
RAID 2-28 , 3-13
RAMCE/ 2-27 , 3-12 , 5-6
RAMOE/ 3-12 , 5-6
RAMWE[1:0]/ 3-12 , 5-6
RBIAS 3-10
read streaming 2-18
received master abort (from master) bit 4-5
received split completion error message bit 4-29
received target abort (from master) bit 4-6
register
cache line size 4-8
capabilities pointer 4-16
class code 4-7
command 2-17 , 4-3
device ID 4-3
diagnostic read/write address 4-39
diagnostic read/write data 4-38
expansion ROM base address 4-15
header type 4-9
host diagnostic 4-36
host interrupt mask 2-15 , 3-7 , 3-8 , 4-41
host interrupt status 4-40
I/O base address 4-9
interrupt line 4-17
interrupt pin 4-17
latency timer 4-8
maximum latency 4-18
memory [0] high 4-10
memory [0] low 4-10
memory [1] high 4-11
memory [1] low 4-11
message address 4-25
message control 4-23
message data 4-26
message upper address 4-25
minimum grant 4-18
MSI capability ID 4-22
MSI next pointer 4-23
PCI memory [1] address map 4-33
PCI-X capability ID 4-26
PCI-X command 4-27