Avago Technologies LSI53C1020 - Manual (Page 41)

PCI Functional Description 2-15
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
2.3.3 PCI Arbitration
The LSI53C1020 contains a bus mastering function for the SCSI function
and for the system interface. The system interface bus mastering
function manages DMA operations as well as the request and reply
message frames. The SCSI channel bus mastering functions manage
data transfers across the SCSI channel.
The LSI53C1020 uses a REQ/-GNT/ signal pair to arbitrate for access to
the PCI bus. To ensure fair access to the PCI bus, the internal arbiter
uses a round robin arbitration scheme to decide which of the two internal
bus mastering functions can arbitrate for access to the PCI bus.
2.3.4 PCI Cache Mode
The LSI53C1020 supports an 8-bit Cache Line Size register. The
Cache Line Size register provides the ability to sense and react to
nonaligned addresses corresponding to cache line boundaries. The
LSI53C1020 determines when to issue a PCI cache command (Memory
Read Line, Memory Read Multiple, and Memory Write and Invalidate), or
PCI noncache command (Memory Read or Memory Write command).
2.3.5 PCI Interrupts
The LSI53C1020 signals an interrupt to the host processor either using
PCI interrupt pins, INTA/ and ALT_INTA/, or using Message Signaled
Interrupts (MSIs). If using the PCI interrupt pins, the Interrupt Request
Routing Mode bits in the
Host Interrupt Mask register configure the
routing of each interrupt to either the INTA/ and/or the ALT_INTA/ pin.
If using MSI, the LSI53C1020 does not signal interrupts on INTA/ or
ALT_INTA/. Note that enabling MSI to mask PCI interrupts is a violation
of the PCI specification. The LSI53C1020 supports one requested
message and disables MSI after the chip powers up or resets.
The Host Interrupt Mask register also prevents the assertion of a PCI
interrupt to the host processor by selectively masking reply interrupts and
system doorbell interrupts. This register masks both pin-based and MSI-
based interrupts.