Host interrupt mask, Host interrupt, Mask – Avago Technologies LSI53C1020 User Manual
Page 119: Register: 0x34
I/O Space and Memory Space Register Descriptions
4-41
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Register: 0x34
Host Interrupt Mask
Read/Write
The
register masks and/or routes the interrupt
conditions that the
register reports.
Reserved
[
31:10]
This field is reserved.
Interrupt Request Routing Mode
[9:8]
This field routes PCI interrupts to the INTA/ or ALT_INTA/
pins according to the bit encodings in the following table.
If the host system enables MSI, the LSI53C1020 does
not signal PCI interrupts on the INTA/ or ALT_INTA/ pins.
Reserved
[7:4]
This field is reserved.
Reply Interrupt Mask
3
Setting this bit masks reply interrupts and prevents the
assertion of a PCI interrupt for all reply interrupt condi-
tions.
Reserved
[2:1]
This field is reserved.
Doorbell Interrupt Mask
0
Setting this bit masks System Doorbell interrupts and
prevents the assertion of a PCI interrupt for all System
Doorbell interrupt conditions.
31
10 9
8
7
4
3
2
1
0
Host Interrupt Mask
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
1
X
X
1
Bits [9:8] Encodings
Interrupt Signal Routing
0b00
INTA/ and ALT_INTA/
0b01
INTA/ only
0b10
ALT_INTA/ only
0b11
INTA/ only