Avago Technologies LSI53C1020 - Manual (Page 169)

Index IX-9
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
PCI-X next pointer 4-27
PCI-X status 4-29
power management bridge support extensions
4-22
power management capabilities 4-20
power management capability ID 4-19
power management control/status 2-16 , 4-21
power management data 4-22
power management next pointer 4-19
reply queue 4-42
request queue 4-42
revision ID 4-7
status 4-5
subsystem ID 4-14
subsystem vendor ID 4-13
system doorbell 4-34
test base address 4-37
vendor ID 4-3
write sequence 4-35
register map A-1
PCI configuration space 4-2
PCI I/O space 4-32
reliability 1-11
reply
message 2-7
reply free FIFO 2-7
reply interrupt 2-15
reply interrupt bit 4-40
reply interrupt mask bit 4-41
reply message 2-5 , 2-7 , 2-15 , 4-42
reply MFA 4-42
reply post FIFO 2-7 , 4-40
reply queue register 4-42
REQ/ 2-15 , 3-6 , 5-6
REQ/ACK offset, 2-18
REQ64/ 3-6 , 5-5
request 2-15
request message 2-5 , 2-7 , 2-15
request MFA 4-42
request post FIFO 2-7
request queue register 4-42
requester ID 4-30 , 4-31
reset adapter bit 4-37
reset history bit 4-36
reset input timing 5-10
revision ID register 4-7
rise and fall time test condition 5-8
ROM 2-5 , 2-23
ROM expansion enable bit 4-15
ROM size 3-19 , 3-21
RST/ 3-4 , 5-9
RTCK_ICE 2-30 , 3-14 , 5-6
RTI 2-18
RTI bit 2-21
S
SACK+- 3-11 , 5-3 , 5-4
SATN+- 3-11 , 5-3 , 5-4
SBSY+- 3-11 , 5-3 , 5-4
SCAN_MODE 3-15 , 3-22 , 5-6
SCANEN 3-15 , 3-22 , 5-6
ScanRstDis 3-15
SCD+- 3-11 , 5-3 , 5-4
SCLK 3-9 , 5-6 , 5-9
SCSI
bus interface 2-6
bus mastering functions 2-15
channel control signals 3-11
channel module 2-5 , 2-6
CLK 3-9
clock 3-9
core 2-6
CRC 2-21
datapath engine 2-6
DIFFSENS signal 5-4
domain validation 2-22
driver signals 5-3
DT clocking 1-2 , 2-18
information unit transfers 2-20
input filtering 5-8
interrupt steering logic 1-10
ISI 2-18
LVD 2-22
paced transfers 2-18
packetized transfers 2-20
parallel protocol request 2-18 , 2-21
performance 1-9
PPR 2-18 , 2-21
precompensation 2-20
QAS 2-18 , 2-21
quick arbitration and selection 2-21
receiver signals 5-4
SE 2-22
single-ended 2-22
skew compensation 2-21
synchronous transfer 2-18